The present invention generally relates to high-temperature superconductor Josephson junctions, and in particular to high-temperature superconductor hetero-epitaxial Josephson junctions.
With the steady demand for faster and more efficient communication and processing systems, many manufacturers wish to utilize high-temperature superconductor (HTS) components in digital circuits because of low power consumption and operational speed of HTS components. In particular, HTS Josephson junctions and Superconductive Quantum Interference Devices (SQUID) incorporating HTS Josephson junctions are principally used as active devices in various circuit families such as single-flux quantum and series array interferometer logic circuits.
Existing HTS Josephson junctions are fabricated by depositing an epitaxial C-axis HTS and dielectric bilayer on a substrate or dielectric layer. The layers are etched at a shallow angle by ion milling to create an etched edge, and then a thin epitaxial non-superconducting barrier and a HTS layer are sequentially grown over the etched edge to form a junction. Junction characteristics are controlled by the composition and thickness of the barrier, and the interfaces between the barrier film and the two HTS layers.
Existing HTS Josephson junctions have several disadvantages however. One such disadvantage is due to the etching process which damages and exposes the etched edge of the lower YBCO layer to contamination and enhanced oxygen loss. The etched edge is contaminated by litho chemicals, chemical cleaning agents, redeposition during ion milling, and gas absorption during handling and wafer transfer. The variability of the etched profile, the physical damage from ion milling or other etching, and contamination of the edge severely compromise electrical quality, reproducibility, and yield of the junction.
Another disadvantage of existing HTS Josephson junctions is that their fabrication process does not allow integration of the junctions with other circuit elements to meet the requirements of robust high performance circuits.
Yet another disadvantage of existing HTS Josephson junctions is due to anisotropy and short coherence length of HTS materials such as YBCO which hinder formation of junctions and low-resistance contacts by utilizing current flow in the a/b-crystallographic directions. It is highly desirable to produce high quality ohmic contacts between c-axis HTS films and resistive films for integrated resistors and input/output (I/O) contact pads. It is also desirable to produce high quality superconducting contacts between different c-axis HTS films of an integrated circuit structure.
A further disadvantage of existing HTS Josephson junctions is lack of planarized topology junctions. Planar junctions simplify processing, improve electrical performance, and increase circuit robustness and yield.
There is, therefore, a need for a method of fabricating a HTS Josephson junction with high electrical quality, reproducibility, and yield. There is also a need for such a method to allow integration of the junctions with other circuit elements to meet the requirements of robust high performance circuits. There is also a need for such a method to facilitate formation of junctions and low-resistance contacts by utilizing current flow in the a/b-crystallographic directions. There is also a need for a planar HTS Josephson junction and a method of fabricating such a planar junction.